Industry Trend（May 25）

Russia completed its first domestic mask aligner, and it is capable of producing 350nm chips

In the wave of independent scientific and technological innovation, Russia has made a major breakthrough. According to the report of Tass, the Deputy Minister of Industry and Trade of the Russian Federation announced during the CIPR 2024 conference that Russia’s first domestic mask aligner has been manufactured and is being tested in Zelenograd. This milestone means that Russia has taken a solid step in the field of semiconductor manufacturing. At the conference, the Deputy Minister further revealed Russia’s mask aligner R&D plan. He said that Russia plans to develop a mask aligner that can support the 130nm process by 2026, and it will represent another great advancement of Russia in terms of technology. What is more remarkable is that the Institute of Applied Physics Federal Research Center, Russian Academy of Sciences (IPF RAS) has put forward an ambitious plan, claiming that it will put its 7nm chip mask aligner into full production in 2028.

This series of R&D plans not only shows Russia’s determination to pursue independence and innovation in the high-tech field but also implies that the landscape of global mask aligner market may greet new changes. As Russia continues to strengthen the construction of the local chip industry chain, it has a rapid development momentum in the field of chip semiconductor.

Comments:

Although the 350nm process lags behind compared with the current international mainstream advanced processes (such as 5nm and 7nm), it still has important practical value. In the fields such as automobile, energy, telecommunications, 350nm process chips can meet many applications due to its mature, stable and cost-effective characteristics. For example, all the sensors and controllers used in automotive electronic systems, energy management and basic communication facilities can use such chips to achieve efficient and reliable operation.

Due to the ongoing technical blockade by western countries, especially the export sanctions on lithography equipment suppliers, the Russian government drew up a great development blueprint for its chip industry. This successful manufacturing of 350nm mask aligner not only shows Russia’s independent innovation ability in the field of science and technology but also injects strong impetus into the localization process of its chip industry.

Company Trend（May 27）

Elon Musk works with Nvidia to build Gigafactory of Compute

Recently, xAI, Elon Musks AI startup, announced an ambitious plan: it will purchase 100,000 Nvidia’s H100 GPUs to build an unprecedented "Gigafactory of Compute". This measure will greatly enhance its AI chatbot, Grok, and will challenge leading enterprises such as OpenAI and Google in the field of AI. It is reported that this supercomputer is expected to be put into operation in the fall of 2025, and its computing power will be at least four times that of the largest CPU cluster at present. Therefore, it can provide strong support for xAIs R&D in the field of AI. It is worth mentioning that this project may also involve cooperation with Oracle, a database giant, which further enhances its technical strength and industry influence. At the same time, the future version of Grok, as a core product of xAI, is estimated to require around 100,000 GPUs, which shows that the company has a long-term planning and huge investment in the field of AI.

Comments:

Nvidia is about to launch a new generation of H200 and Blackwell architecture-based B100 and B200 GPU. However, xAI chose to use the previous generation H100 GPU to build a supercomputer, which reflects the companys robust strategy in technology selection and recognition of the performance of H100. H100 GPU has been highly recognized in the AI data center chip market, and its powerful computing power provides a solid foundation for the training of large language models.

xAI plans to build a "Gigafactory of Compute" using H100, which further demonstrates its ambition in the field of AI. This will give a strong impetus to the IC industry and accelerate the upgrading of related technologies and products. In addition, it also indicates that AI competition has entered a new stage, and technology, capital and market will be combined closer, thus promoting the development of the whole industry to a higher level.

Company Trend（May 30）

ASML sets density record of EUV mask aligner by breaking through technical barrier

Recently, at imec’s ITF World 2024, ASML, the world’s leading lithography equipment manufacturer, has announced that its High-NA EUV lithography machine set a new record of chip density and can print chips with an 8nm resolution. This technical breakthrough not only indicates that ASML has made great progress in the field of lithography technology, but also injects new vitality into the development of the global semiconductor manufacturing industry.

It was reported that the former President and CTO of ASML revealed at the conference that after further technical adjustment and optimization, ASMLs High-NA EUV mask aligner has successfully printed 8nm line patterns in the production environment, breaking the previous record of 10nm resolution in early April. At the same time, he put forward the idea of developing tools for manufacturing Hyper-NA chips, and shared a plan for reducing the manufacturing cost of EUV chips.

It is worth mentioning that ASML plans to reduce EUV chipmaking costs by increasing the speed of future ASML tools. ASML plans to boost the speed of future ASML tools to 400 to 500 wafers per hour (wph), more than double the current peak of 200 wph. This will improve production capacity, reduce production costs and bring greater competitive advantages to chip manufacturers.

In addition, ASML also put forward a series of EUV tools with modular and unified design, which will bring more flexibility and efficiency to future chip manufacturing. This innovative design will not only help shorten the product development cycle, but also further improve the quality and output of chip manufacturing.

Comments:

ASML’s latest technical breakthrough is a major milestone for the entire semiconductor industry. The successful application of High-NA EUV lithography technology not only set a new record of chip density but also indicated that this technology will become the core of chip manufacturing in the future. This innovation not only reflects the excellent technical strength of ASML, but also provides a new impetus for the progress of the global semiconductor industry. At present, there are only two mask aligners of this type in the world. The two machines have been put into use in ASML headquarters and Intels wafer plant, respectively, which shows that a new era of semiconductor manufacturing technology is coming. Looking into the future, we expect that ASML continues to lead the industry innovation, brings more technical surprises and breakthroughs, and promotes the further development of the entire semiconductor industry.

Market Trend（May 31）

Chip giants united to launch UALink to challenge Nvidias NVlink monopoly

Recently, major tech corporations including AMD, Broadcom, Cisco, Google, HPE, Intel, Meta, and Microsoft have joined forces to develop Ultra Accelerator Link (UALink), aiming to challenge Nvidia NVLink’s dominance in the AI data center link technical field. UALink is an open standard designed to establish a unified code for interconnection between AI accelerators. to enable the openness and diversity of the accelerator ecology of data centers.

The launch of UALink marks a breakthrough of the IC industry in terms of interconnection technology. With the rapid development of AI technology, the demand for computing power from data centers is increasing day by day, and high-speed and low-latency interconnection technology has become a key technology. Although Nvidia NVLink dominates a leading position in the industry, its closeness limits the development space of other manufacturers. UALink has brought more possibilities to the industry.

The core advantage of UALink lies in its openness and scalability. By formulating a unified technical code, UALink will allow accelerator modules of different manufacturers to work in a cooperative manner, thus improving the flexibility and customization of the system. In addition, UALink also enables high-speed and low-latency data transmission to meet the needs of large-scale AI applications.

Comments:

The launch of UALink marks a breakthrough of the IC industry in terms of interconnection technology. The technology eliminated the dominance position of NVIDIA NVLink and brought more vitality and innovation space to the entire industry. The openness and scalability of UALink is expected to promote the healthy development of accelerator ecology of data centers and promote technological innovation and industrial upgrading. At the same time, it presents more options for ultra-large enterprises to help reduce the construction cost of systems and improve operational efficiency. It is expected that UALink will play a greater role in the future and promote the sustainable development of the IC industry.

Domestic Trend

Zhangjiang chip testing public service platform to come soon（May 31）

According to the news of the official Wechat account of Zhangjiang Inno Park, Zhangjiang chip testing public service platform will be available soon.

According to the report, the platform is jointly built by Zhangjiang Inno Park and Sino IC Technology Co., Ltd., and it will provide more efficient and convenient testing services for related IC design enterprises in the park to speed up the chip manufacturing process from design to mass production. The platform will provide various services such as DFT design service, test scheme design and software & hardware development, engineering test, small batch test, reliability test, test data, homemade test equipment verification, public course training, and packaging technology consultation.

In the future, Zhangjiang Inno Park will take the opportunity of building a public chip testing service platform to collaborate with industrial ecological partners to make innovation and rely on the multi-dimensional resources of top enterprises in sub-sectors to jointly promote the rapid growth of tech-innovation enterprises.

TASC announced separation of its 8-inch GaN product business group（May 28）

On May 28th, Taiwan-Asia Semiconductor Corporation (TASC) announced that it had approved the previously proposed 8-inch GaN (gallium nitride) business separation plan through the resolution of the shareholders meeting, and its subsidiary Wuxi Guanya Refrigeration Technology Co., Ltd. (LNEYA) undertook the business. At the same time, Yi Guanjun, general manager of LNEYA, will be transferred to take the post of general manager of TASC to be responsible for its future 8-inch GaN products related business.

According to Yi Guanjun, the initial GaN production capacity of TASC will focus on 6-inch wafers. At present, the 6-inch GaN production line still remains at TASC, and it has to produce sensing components simultaneously. TASC has completed the dynamic reliability test of its first generation 650V 150 milliohm D-modeHEMT and sent samples to customers at home and abroad. It accepts orders in the mode of wafer foundry and manufacture OEM products for its subsidiary LNEYA.

At present, all the equipment for LNEYA’s first 8-inch production line has been moved in, and it is expected that the development of related components will start at the beginning of Q3 this year, and the products will pass the verification before the end of the year. The produced components of various specifications will use the driver chips made by local design companies. With the advanced BGBM of Taiwan and support of packaging and testing companies, it will produce power modules and systems for sale.

Zhuhai Zestsemi taped out 28nm FPGA（May 31）

According to the news of its official Wechat account, Zhuhai Zestsemi Co., Ltd. Recently announced that it had successfully taped out 28nm FPGA.

According to the report, the CERES-1FPGA of Zestsemi benchmarks the international mainstream architecture of 28nm FPGA, including 600,000 logic gates, 3,750 six-input logic lookup tables, 100 user IOs, 180KB on-chip storage, and 10 DSP units, achieving pin compatibility and bit stream compatibility. By matching KUIPER-1 demo board of Zestsemi, the chip can seamlessly dock with international mainstream development platforms and ecologies to replace imported chips and demo boards. The successful taping out of MPW verified the maturity and reliability of Zhuhai Zestsemi’s 28nm FPGA, and Zestsemi will promote the mass production of 28nm FPGA in the next step.

According to the data, Zhuhai Zestsemi Co., Ltd. was established in 2021, and its business covers FPGA, demo boards, IP and EDA. The companys high-performance IC design technology provides users with high-performance computing power at the lowest cost. The founder of the company cooperated with the academicians of Intel to develop high-performance IC design technology, which has been applied in Intel’s design process. In addition, the founder cooperated with Cadence Strategic Planning to jointly develop IC safety design technology.