Company Trend(Nov. 13)
TSMC expands advanced packaging capacity to meet urgent orders from leading customers
TSMC is actively accelerating its CoWoS packaging capacity to meet surging demand. It was reported that TSMCs leading customers such as NVIDIA, AMD, and Amazon have placed a large amount of urgent orders. To this end, TSMC has to urgently purchase more CoWoS equipment from suppliers and increased orders by up to 30% based on its original production increase target, indicating that the AI fever continues. According to report, TSMC is seeking support from equipment suppliers and requires them to increase supply of CoWoS equipment, which is expected to be delivered and installed in H1 next year. Related equipment manufacturers are very busy now. Apart from winning TSMCs original orders of machines for expanding production capacity, they have received more orders by up to 30%. As TSMCs H2 revenue is increasing significantly, related equipment manufacturers are holding more orders in hand, which will not be completed until H1 next year. Insiders said that currently TSMCs CoWoS packaging capacity is up to 12,000 units. After its previous production expansion, TSMCs monthly capacity of CoWoS will be increased to between 15,000 and 20,000 units. After installing more equipment, TSMC will increase its capacity to 25,000 units and even to 30,000 units per month, which enables TSMC to receive more orders of AI chips.
TSMCs five major customers are placing more orders, revealing that AI applications have landed in many fields, driving the surging demand for chips such as graphics processors (GPU) and AI accelerators. Quanta Computer, the representative foundry of AI servers, has publicly warned before that the shortage of AI chips is the main reason that the shipment momentum of the AI supply chain is suppressed now. At present, the biggest barrier to the supply of AI chips is the lack of advanced packaging capacity. With the faster expansion of TSMCs advanced packaging capacity beyond expectation, the shortage of AI chips will be alleviated, which will drive the entire AI supply chain to show stronger explosiveness. TSMC has been expanding its facilities at plants including Zhuke, Zhongke, Nanke, and Longtan, so as to increase CoWoS production capacity, and TSMCs Zhunan Advanced Packaging and Testing Plant AP6 will build CoWoS and SoIC packaging production lines at the same time. By actively expanding its CoWoS advanced packaging capacity, TMSC hopes to ease the pressure of insufficient production capacity after H2 2024.
Market Trend(Nov. 13)
Wafer foundry mature process greatly reduces prices, sparking a fierce price war
Wafter foundry mature process practitioners are facing a war of defending the capacity utilization rate of 60%. According to report, in order to save the utilization rate of production capacity, UMC, Vanguard International Semiconductor Corporation, PSMC and other main manufacturers have slashed their quotations for Q1 next year, down by double-digit percentage, even down 15% to 20% for special customers. The industry pointed out that since TSMC has advanced processes as backup, it can sell advanced chips together with chips of mature processes. In addition, the foundry price of mature processes did not rise as dramatically as that of other related industries previously, at present customers can still accept TSMCs pricing strategy, which relatively supports the price of TSMCs mature process. As for UMC, it is expected its capacity utilization rate will drop from 67% in the previous quarter to 60% to 63%, which is the lowest for a single quarter in recent years. Affected by the continuous correction of the capacity utilization rate, the gross profit margin of the company will slump from 35.9% in the previous quarter to 31% to 33%, returning to the level at the initial outbreak of COVID-19 in 2021. In response to this price issue, UMC responded that, as the its statement in the Earnings Call a few days ago, the price of 8"wafers has dropped sharply while the price of 12"wafers has not been adjusted. According to insiders of the supply chain, UMC has offered a 5% discount to major customers in this quarter to consolidate customers ordering momentum. Considering the sluggish demand in Q1 of next year, in order to attract customers to increase tape-out, UMC will decrease its quotation to a double-digit percentage. As for Vanguard International Semiconductor Corporation, insiders of the supply chain revealed that its quotation is expected to drop by 5% in the H2 of the year, and customers with large amount of tape-out will have a 10% discount, even down with a single-digit percentage to a double-digit percentage in Q1 next year.
This quotation correction has led to the new low of the foundry price of mature process wafers, which has affected the gross profit margin and profit trend of related industries. According to industry sources, only the price of TSMCs mature process is still firm, and almost no other manufacturers are spared from the wave of price cutting. The industry defends the capacity utilization rate and they have started a fierce battle of cutting quoted prices. The business of mature process wafers performs badly, and the related capacity utilization rate plumps rapidly. In order to defend the capacity utilization rate and market share, and maintain a certain scale of production and economy size, it is necessary for wafer foundries to slash their quoted prices. Even if there are signs of recovery in the PC and mobile phone markets recently, the external factors such as inflation are still significant for the client side. Especially in the past year, almost all of the players were reducing their inventories, and they are afraid of falling into the mire of reducing inventory. Therefore, they still hold a conservative strategy in taping out wafers. At present, the orders have restored to only about 30% to 40% of the orders placed before the outbreak of COVID-19. This makes wafter foundries feel anxious and strengthen efforts to slash prices to prevent their orders from flowing to rivals, which may lead to a lower capacity utilization rate.
Company Trend(Nov. 14)
TSMC announces new progress in 2nm process node
TSMC has decided to set up a 2-nm advanced process fab in Kaohsiung and has given up setting up a 1.4-nm process fab in Longtan Science Park in Taoyuan City. Therefore, the Kaohsiung City Government is also actively striving to win over setting up the fab, saying that TSMC is following the original schedule and plan without any change. In August 2023, TSMC officially announced that it would build a 2 nm advanced process fab in Kaohsiung after giving up its original planned two fabs of 7 nm and 28 nm process nodes. According to TSMCs plan, the 2-nm process fab in Kaohsiung will be ready for mass production in 2025, adopting a nanosheet transistor structure. At the same time, TSMC has incorporated backside power delivery network (PDN) into its 2nm-class process, which can be used for high-performance computing. According to its plan, TSMC will launch the 2nm process in H2 2025 and start mass production in 2026. As for the plan of TSMC, the Deputy Director of the Economic Development Bureau of Kaohsiung City Government said that TSMC is following the original schedule and plan without any change. In addition, in view of TSMCs giving up setting up a 1.4-nm fab in Longtan Science Park, Kaohsiung City Government is actively striving to win over setting up the fab there.
TSMC takes lead in developing advanced process and its 2 nm process R&D derives from its self-breakthrough rather than competitive pressure. The biggest R&D bottleneck of 2nm process node will be the yield, and there must be suitable equipment and materials to support it. After its R&D breakthrough, TSMC also faces the challenges such as whether customers can pay the bill, and even whether there is so much demand for emerging applications in the future or how many products need to adopt 2 nm process node in mass production in 2025. In 2025, what kind of electronic products will adopt 2nm process node? The first application that everyone thinks of is metaverse, because the arrival of the 5G era will drive smart wear, including smart glasses. The second is automotive electronics. The more complete the self-driving function, the faster the operation speed with lower power consumption. However, there are many variants for consumers to really pay the bill in 2025. That’s why TSMC is so conservative.
Company Trend(Nov. 16)
Microsoft unveils its self-developed AI chip
The rumor that Microsoft is working on its own artificial intelligence chip has never stopped. At the annual Microsoft Ignite 2023, Microsoft finally launched its Azure Maia 100, an AI chip for data center, and Azure Cobalt 100, a cloud computing processor. Azure Maia is an AI accelerator chip, used for AI computing tasks such as OpenAI model, ChatGPT, Bing, GitHub Copilot, etc., and Azure Maia 100 is the first generation product of this series, which is produced with the 5nm process technology. Azure Cobalt is a 128-core Arm-based processor for cloud computing. Compared with the previous generations of Azure Arm-based chips, Azure Cobalt delivers a 40% improvement of efficiency and provides supports for Microsoft Teams and Azure SQL. Both chips are produced by TSMC, and Microsoft is already designing the second generation version of the two types of chips. The Microsoft Corporate Vice President for Azure Hardware Systems and Infrastructure (AHSI) who led the team to develop new chips pointed out that Microsoft has tested new AI chips in Bing and Office products, and Microsofts main AI partner, ChatGPT developer OpenAI, also tested the new chip on GPT-3.5 Turbo. It is expected that Microsoft will officially use Azure Maia and Azure Cobalt in its data centers early next year and the two new chips will become part of Azure cloud computing services. In addition, for the large operation scale of Microsoft, to optimize and integrate every layer of its hardware to maximize computing performance, diversify its supply chain, Azure Maia and Azure Cobalt can give customers new infrastructure choices.
Self-developed chips can help a company gain hardware performance and price advantages and avoid its excessive dependence on any chip supplier. At present, the AI industry is highly dependent on NVIDIA GPU, which brings the problem of dependence onto the table. Amazon and Google have made concrete achievements in self-developed chips. In 2015, Amazon acquired Israeli chip company Annapurna Labs to provide customers with cloud and AI chip services, while Google has allowed customers to adopt its self-developed chip TPU since 2018. As a result, Microsoft is finally catching up with them. In addition, to supplement custom chips, Microsoft is expanding its partnership with chip suppliers to provide customers with infrastructure options.
Trends of some domestic industries
1.HGC completes its semiconductor device center expansion project(Nov. 13)
According to the report of its official Wechat account, HGC (Wuhan) Technology Co., Ltd. (“HGC”) held a grand ceremony of unveiling its semiconductor device center at Wuhan Eastlake Free Trade Zone, officially announcing the completion of its high-end optical device capacity expansion project. It is reported that the semiconductor device center expansion project is another important measure of HGC to ramp up capacity and improve mass production & delivery capacity after its chip mass production base was completed and put into production at the end of March this year. The center will undertake the R&D and manufacturing of HGCs main products such as vehicle-grade optical source, new light source - Mini-LED, UV light source and IR optical device. It is of strategic significance for HGC to continue to deepen its vertical integration strategy of "chip/packaging/testing/application", further strengthen the performance and cost advantages of high-end optical source products, and better meet the demands rapidly rising in emerging markets. It is learned that HGC, as a leading IDM manufacturer of high-end semiconductor optical sources in China, has gained a leadership position at the subdivided fields with high thresholds by means of its continuous technological innovation and R& of products within several years after its establishment. At the same time, it continuously expands its market share based on differentiated competitive advantages.
2.DJEL unveiled its integrated yield solution at ICCAD2023(Nov. 14)
The 29th CSIA-ICCAD 2023 Annual Conference & Guangzhou IC industry Innovation and Development Summit (ICCAD) was successfully held in Guangzhou. Dongfang Jingyuan Electron Co., Ltd.(“DJEL”) was invited to participate in the summit to showcase its multiple products and technologies of the EDA industry. At the same time, DJEL delivered a wonderful speech at the FOUNDRY and Technology Forum, sharing its forward-looking integrated yield solution HPOTM and the latest technological development results. From the very beginning, DJEL aimed at the development pain points of the industry, focused on the field of IC yield management, and proposed a unique DTCO solution-HPOTM (Holistic Process Optimization), a technology route of maximizing yield and product design concept. With the seamless link of nano-scale testing equipment and core EDA tool chain as its core technical advantage, HPOTM fills the information gap in the process of chip design and manufacturing, improves efficiency, reduces manufacturing cost, and realizes the computability, visibility, measurability and seamless link in the chip manufacturing process, making the chip manufacturing process evolve from "art" to "science" to "intelligence”, which ultimately lowers the threshold of chip manufacturing.
3.Forehope plans to invest in high-density and hybrid IC packaging and testing project(Nov. 15)
According to the report of SEMI, Forehope Electronic（Ningbo) Co., Ltd. ("Forehope") announced in the morning of November 15 that it plans to invest in the high-density and hybrid IC packaging and testing project with its holding subsidiary Forehope Semiconductor as the main carrier to implement the project to promote its strategic planning for long-term development, expand its market share in the IC packaging and testing industry, and enhance its core competitiveness. It is reported that this project is planned to be built at rented facilities, where some production workshops need to be renovated according to the requirements of Class 100 clean room; in addition, Forehope plans to purchase advanced production equipment and supportive equipment for the project. It is estimated that the project will provide high-density and hybrid IC testing for 87 million chips after put into production. It is learned that this project will help to enhance Forehopes competitive advantage in terms of advanced packaging and testing technology, including FC products, meet the growing demand of customers for related technology, and lay a foundation to undertake high-end product orders in the future. This investment project, in line with the overall development strategy of Forehope, will help expand its market share in the IC packaging and testing industry and enhance its core competitiveness.